Accession Number : ADA626736


Title :   Floating Point Multiply-Add-Subtract Implementation


Descriptive Note : Patent application, Filed 7 Nov 2014


Corporate Author : NAVAL UNDERSEA WARFARE CENTER DIV NEWPORT RI


Personal Author(s) : Powell, Makia


Full Text : http://www.dtic.mil/get-tr-doc/pdf?AD=ADA626736


Report Date : 07 Nov 2014


Pagination or Media Count : 22


Abstract : A floating point multiply and addition/subtraction implementation is provided. Two operands are received in a standard floating point format with a code selecting a mathematic operation from addition, subtraction, and multiplication. Result mantissas and exponents are calculated simultaneously for all operations. The implementation simplifies computation of a result mantissa by dropping the least significant bits of the operands before computing the result. Underflow and overflow errors are shown by two extra bits in the exponent portion of the result. The mantissa result and the exponent result are selected by providing the operation code to a mantissa multiplexer and an exponent multiplexer. The selected mantissa and exponent are combined as output.


Descriptors :   *FLOATING POINT OPERATION , COMPUTATIONS , PATENT APPLICATIONS


Subject Categories : Operations Research
      Computer Programming and Software


Distribution Statement : APPROVED FOR PUBLIC RELEASE