Accession Number : ADA208371


Title :   Easily Testable PLA-Based Finite State Machines


Descriptive Note : Memorandum rept.,


Corporate Author : MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER


Personal Author(s) : Devadas, Srinivas ; Ma, Hi-Keung T. ; Newton, A. R.


Report Date : MAR 1989


Pagination or Media Count : 9


Abstract : This paper outlines a synthesis procedure, which beginning from a State Transition Graph description of a sequential machine, produces an optimized easily testable PLA-based logic implementation. Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck- at fault mode. For PLAs, and extended fault model called the crosspoint fault model is used. This paper, proposes a procedure of constrained state assignment and logic optimization which guarantees testability for all combinationally irredundant crosspoint faults in a PLA-based finite state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a Scan Design methodology. We present results which illustrate the efficacy of this procedure--the area/ performance penalties in return for easy testability are small.


Descriptors :   *CIRCUIT TESTERS , FAULTS , METHODOLOGY , OPTIMIZATION , MODELS , SYNTHESIS , GRAPHS , TEST METHODS , SEQUENCES , GUARANTEES , CIRCUIT INTERCONNECTIONS , MACHINES , ACCESS , TRANSITIONS , CIRCUITS , LOGIC , SCANNING , TEST AND EVALUATION


Subject Categories : ELECTRICAL AND ELECTRONIC EQUIPMENT


Distribution Statement : APPROVED FOR PUBLIC RELEASE