Accession Number : ADA208337


Title :   Fault Tolerant VLSI (Very Large-Scale Integration) Design Using Error Correcting Codes


Descriptive Note : Final technical rept. Mar 1987-1988


Corporate Author : SYRACUSE UNIV NY


Personal Author(s) : Hartmann, C R ; Lala, P K ; Ali, A M ; Ganguly, S ; Visweswaran, G S


Full Text : http://www.dtic.mil/dtic/tr/fulltext/u2/a208337.pdf


Report Date : Feb 1989


Pagination or Media Count : 67


Abstract : Very Large-Scale Integration (VLSI) provides the opportunity to design fault tolerant, self-checking circuits with on-chip, concurrent error correction. This study determines the applicability of a variety of error-detecting, error-correcting codes (EDAC) in high speed digital data processors and buses. In considering both microcircuit faults and bus faults, some of the codes examined are: Berger, repetition, parity, residue, and Modified Reflected Binary codes. The report describes the improvement in fault tolerance obtained as a result of implementing these EDAC schemes and the associated penalties in circuit area.


Descriptors :   *ERROR CORRECTION CODES , *CHECKOUT PROCEDURES , *MICROCIRCUITS , ERRORS , TOLERANCE , SELF OPERATION , BINARY NOTATION , PARITY , CORRECTIONS , FAULTS , INTEGRATION , CODING , REFLECTION , CIRCUITS


Subject Categories : Electrical and Electronic Equipment
      Computer Programming and Software


Distribution Statement : APPROVED FOR PUBLIC RELEASE